FIG. 15 is a block diagram showing a conventional system to which a POST is applied. In FIG. 15, the system includes partitions #0 and #1. The partition #0 is constituted by SB #0 and SB #1 which are POST diagnosis targets. Similarly, the partition #1 is constituted by SB #2 and SB #3. Further, the system of FIG. 15 includes an SP (control service processor) 1 that controls the entire system constituted by the partitions and SBs.
The SBs #0 to #3 each include a CPU 2, an FMEM (Flash Memory) 3 for storing a POST, a bus switch SC/XB 6 of a system bus for connecting to another SB in the same partitions so as to allow the respective SBs to work in a collaborative manner, and an I/F section 4 serving as an interface with the SP 1.
Each of the partitions #0 and #1, is constituted by combining resources (CPU and the like) in one or more SBs constituting the database or server and a unit providing an environment where its own OS runs.
The SP 1 is connected to the SBs #0 to #3, respectively, through the system control bus and I/F sections 4 of the SBs. In the example of FIG. 15, the SP 1 has a redundant configuration with two SPs #0 and #1, each of which has a CPU 8 and is configured to be able to operate according to a program stored in an FMEM 7. In each SB, the CPU 2 can directly access the I/F section 4 and FMEM 3.
The conventional operation performed in this system will be described below. At normal operation time, the Master-side SP 1 controls the entire system. At maintenance time, control of the system is transferred from the Master-side to slave-side SP1. The POST becomes effective only after the POST is registered in a given partition and the partition is restarted. In a conventional configuration, the CPU 2 on the partitions #0 and #1 rewrites the POST into the FMEM 3 and restarts the partition.
As described above, the SBs #0 to #3 each include the FMEM 3, which is a rewritable memory, in which the POST with a default version number has been written. In the case where the version number of the POST that has been written in the SB differs from the original one for the reason that the SB is replaced with a new one due to a failure or an additional SB is installed, inconsistency occurs between the SBs in the same partition.
In order to prevent occurrence of the inconsistency, the following approach has been taken. That is, whether or not a POST of the same version number has been written in a new SB is confirmed before replacement and, in the case where a POST of a different version number has been written on the new SB, a POST of the same version number is written on the FMEM on the new SB after start-up of the system so that the version numbers of the POSTs used in the SBs in the same partition coincide with each other.
As a technique relevant to the present invention, there is known a technique in which a POST is written from the control service processor to a resource on the CPU side so as to increase the start-up speed of the POST (refer to, e.g., Patent Document 1).    Patent Document 1: Japanese Laid-Open Patent Publication No. 05-265766